The invention relates to a circuit for rapidly resynchronizing a clock with an external clock, the generator of the clock to be synchronized comprising a phase-locked loop supplying the desired clock signal by dividing the frequency of a reference clock signal in a frequency divider the division factor of which is controlled by a phase comparator which detects the deviation between characteristic transitions of the two clock signals to be synchronized.
Such a circuit is, for example, used in the receiver of a data transmission system to obtain a local clock which is in synchronism with the external data clock formed from the received data signal. It is important that, at the beginning of each transmission of the data, the synchronization of the local clock with the external clock is effected as rapidly as possible from the instant at which a signal detection circuit has detected the appearance of a data signal at the input of the receiver. When, on the contrary, no measures are taken, this resynchronization may be slow when the above-mentioned phase-locked loop is used.
The clock frequency to be synchronized for a receiver of a data transmission system is low, for example 2400 Hz. The local clock of this frequency is obtained by dividing a high reference frequency which is generally produced by a quartz oscillator. The phase deviation detected by the phase comparator is corrected at the phase-locked loop in the slow rate of the clocks to be synchronized. The value of each correction (positive or negative) is low and corresponds to one or several periods of the high-frequency reference signal in order to maintain an accurate synchronization between the two clocks. On the other hand, however, the time before synchronization is obtained may be very long as, at the start of each transmission, there is an arbitrary phase relation between the two clocks to be synchronized.
A known means to obtain synchronization rapidly is to reset the counter which constitutes the frequency divider applying the local clock to zero at the instant the first characteristic transition of the external clock signal occurs. This resetting operation produces a characteristic transition of the local clock and the two clocks are therefore in synchronism at that instant; thereafter the phase-locked loop operates in the normal manner to keep thereafter the two clocks synchronized.
However, the rapid resynchronizing process cannot be used in all circumstances. In the commercially available integrated circuits which function as the phase-locked loop and which particularly comprise the counter functioning as the frequency divider, there is, for example no input for resetting this counter to zero.